There is an example of one-pulse mode in the TIMx functional description chapters of the reference manual. Neither HAL nor LL is documented in sufficient detail for such everyday requirements. TIM3->CR1 |= TIM_CR1_OPM | TIM_CR1_DIR // enable one pulse mode, downcounting TIM3->CCER |= TIM_CCER_CC3E // Enable PWM output on channel 3 TIM3->CCR3 = 360 - 1 // start the pulse 360 cycles ( = 10 μs ) before the counter reaches 0 TIM_SMCR_SMS_2|TIM_SMCR_SMS_1 // SMS=110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI TIM_SMCR_TS_2|TIM_SMCR_TS_1|TIM_SMCR_TS_0| // TS=111: External Trigger input (ETRF) TIM3->ARR = 0xFFFF // set it to Toff + Ton - 3, as the trigger takes 2 cycles to have an effect It can be changed anytime, when the new Toff value becomes available. The reload (ARR) value should be the sum of Toff and Ton, minus the adjustment required because of the 2 cycles trigger latency.
SET A TIMER FOR 10 40 CODE
I've changed the above code a bit, using the timer in downcounting mode, so that the compare register can be set to a fixed value, which is the number of cycles before the downcounter reaches 0, to start the pulse. other interrupts in the system.Įxact synchronization down to a system clock cycle can be achieved by using a timer trigger input, which can be the timer CH1, CH2, or ETR pin.
EXTI interrupts are not really useful for synchronization, because interrupt latency is variable, maybe between 10-40 cycles, depending on the timing w.r.t.
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